FPGA inžinierius
Apie poziciją
"Sentrycs" misija - sukurti dronais varomą ateitį!
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As a Senior FPGA & System Architecture Engineer, you will drive the end-to-end hardware architecture and implementation of next-generation wireless communications systems. You will lead the design and integration of high-throughput physical layer pipelines across AMD Xilinx RFSoC platforms, high-speed PCIe interfaces, and host GPU acceleration environments—bridging algorithmic signal processing with production-grade SoC hardware infrastructure.
Atlikdami šį vaidmenį:
- Architect & Design: Own the full-chip system architecture on AMD Xilinx RFSoC platforms.
- DSP RTL Implementation: Partner directly with Algorithm Engineers to translate floating-point MATLAB/C++ models into fixed-point, resource-optimized, and bit-exact SystemVerilog RTL.
- Host & GPU Acceleration Interfacing: Architect and implement high-bandwidth PCIe subsystems connecting the RFSoC to host CPU and GPU accelerators, ensuring deterministic data streaming, low-latency DMA transfers, and reliable link initialization during system boot.
- Verification & Hardware Bring-Up: Lead bit-accurate simulation, hardware emulation, and lab bring-up using Vivado, logic analyzers, and RF test equipment to profile throughput, validate timing closure, and eliminate real-time system bottlenecks.
Reikalavimai
Idealus FPGA inžinierius, kurio ieškome, turėtų turėti
- SoC & FPGA Mastery: Proven, hands-on experience architecting and delivering production designs on AMD Xilinx Zynq UltraScale+ RFSoC or MPSoC platforms.
- HDL & RTL Implementation: Expert-level proficiency in synthesizable SystemVerilog arba Verilog, with a strong focus on high-speed pipelining, timing closure in congested designs.
- Host Interfacing & Data Movement: Demonstrated experience implementing high-bandwidth PCIe subsystems (Gen3/Gen4) and high-throughput DMA engines (e.g., XDMA/QDMA), including link training/enumeration bring-up, boot sequencing, and backpressure management.
Malonu turėti
- RF-DC Subsystem Integration: Hands-on experience configuring and integrating AMD Xilinx RF-Data Converters (multi-gigasample ADCs/DACs) and their associated digital down/up-conversion chains.
- DSP Hardware Design: Strong foundation in implementing fixed-point wireless communications algorithms in FPGA fabric (e.g., polyphase filter banks, multi-rate DDC/DUC, FFT/IFFT, channel estimation, correlation) with efficient DSP slice mapping and dynamic range management.
- Driver & Software Alignment: Familiarity with Linux kernel drivers, user-space drivers (VFIO/UIO, DPDK), or embedded software running on the ARM Processing System to coordinate hardware-software control planes.